Search - rom verilog

[Other] Design_and_verification_verilog_hdl

Description: 设计与验证verilog hdl配套光盘-Design and verification verilog hdl" supporting CD-ROM
Platform: | Size: 2042880 | Author: zhc | Hits:

[VHDL-FPGA-Verilog] rom_table

Description: rom vector table vhdl and Testbench
Platform: | Size: 172032 | Author: KoBin | Hits:

Description: RS(204,188)译码器说明原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_power.mif（ROM初始化文件）。仿真波形： rs_decoder.vwf。-RS (204,188) decoder that the original document: rs_decoder.v (top-level document), SyndromeCalc.v (calculated Syndrome), BM_KES.v (BM key equation solving), Forney.v (Forney algorithm for error-like value), CheinSearch.v (search the wrong location), ff_mul.v (finite field multiplication). ROM and the initialization file: rom_inv.v (inverse operation), rom_power.v (for power calculations) rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization files). Simulation waveforms: rs_decoder.vwf.
Platform: | Size: 14336 | Author: 川天古木 | Hits:

[source in ebook] VerilogHDLdigitalICdesignChapter1to8

Description: 微电子教材《Verilog数字系统设计》美电子工业光盘\Verilog实用范例。-Microelectronics Study \ "Verilog Digital System Design," the United States electronics industry, CD-ROM \ Verilog practical examples。
Platform: | Size: 381952 | Author: qq | Hits:

[Windows Develop] LFSR

Description: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Platform: | Size: 870400 | Author: 风影 | Hits:

[Software Engineering] DDS1

Description: 直接数字频率合成器（Direct Digital synthesizer）是从相位概念出发直接合成所需波形的一种频率合成技术。一个直接数字频率合成器由相位累加器、加法器、波形存储ROM、D/A转换器和低通滤波器（LPF）构成-Direct digital frequency synthesizer (Direct Digital synthesizer) is the concept of direct synthesis from the requirements phase of a waveform synthesizer technology. A direct digital frequency synthesizer by the phase accumulator, adder, waveform storage ROM, D/A converter and low pass filter (LPF) constitute
Platform: | Size: 261120 | Author: wufeng | Hits:

[Other] VerilogHDL

Description: 《基于Verilog HDL的数字系统应用设计》光盘-" Based on Verilog HDL Application of Digital System Design" CD-ROM
Platform: | Size: 40960 | Author: 蔡新林 | Hits:

[Other] VerilogHDL-FPGA

Description: Verilog HDL程序设计实例详解光盘 FPGA-Verilog HDL programming example explanation of CD-ROM
Platform: | Size: 19944448 | Author: 蔡新林 | Hits:

[VHDL-FPGA-Verilog] SPI_controller

Description: SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
Platform: | Size: 8192 | Author: Jerd Hu | Hits:

[3G develop] DDFS_verilog

Description: 直接数字频率综合器，采用ROM压缩法，经过FPGA验证和AISC实现-Direct digital frequency synthesizer, using ROM compression method, validation and AISC through FPGA Implementation
Platform: | Size: 5120 | Author: jessie | Hits:

[VHDL-FPGA-Verilog] VGA_char_ROM_success

Description: Verilog HDL语言编写的基于M4K块配置ROM的字符数据存储VGA显示实验代码，引脚分配适用于21EDA的EP2C8Q208开发板, 详细解说请参见特权同学《深入浅出玩转FPGA》视频教程中的《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》-experimental code written in Verilog HDL language，ROM configuration based on M4K block for the character data storage and VGA display, pin assignment for the EP2C8Q208 21EDA development board, for a detailed explanation you can see 《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》in the book《深入浅出玩转FPGA》.
Platform: | Size: 785408 | Author: LM | Hits:

[VHDL-FPGA-Verilog] LIP2261CORE_rom

Description: Verilog ROM Source code
Platform: | Size: 11264 | Author: jc | Hits:

[VHDL-FPGA-Verilog] mult4x4

Description:
Platform: | Size: 1024 | Author: 李小明 | Hits:

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] dds

Description: 采用verlog编写的tlc5615驱动程序，并利用了rom核实现了dds功能-Using verlog written tlc5615 driver, and use the rom-core functions to achieve a dds
Platform: | Size: 619520 | Author: ranshaoqiang | Hits:

[VHDL-FPGA-Verilog] Circuit-with-a-combination-of-ROM

Description: 用组合电路实现的ROM，采用Verilog HDL语言进行编写。-Circuit with a combination of ROM, using Verilog HDL language for writing.
Platform: | Size: 178176 | Author: 快乐天使 | Hits:

[VHDL-FPGA-Verilog] 256_16_RAM_Block

Description: 本例子实现了一个256*16的ROM块的实现方法，介绍了基本的ROM的verilog HDL编程方法。-This example implements a 256* 16 block of ROM implementation, describes the basic programming of ROM verilog HDL.
Platform: | Size: 266240 | Author: 快乐天使 | Hits:

[VHDL-FPGA-Verilog] verilog-rom

Description: verilog 语言实现的ROM模块的代码。-ROM module verilog language code.
Platform: | Size: 91136 | Author: 张秋光 | Hits:

[VHDL-FPGA-Verilog] Syn_FIFO

Description: 基于Actel公司的开发平台，verilog实现同步fifo设计-Double port ROM verilog realization, based on the development of the Actel development platform based on Actel company development platform, verilog simultaneous fifo design
Platform: | Size: 2820096 | Author: 林鸿海 | Hits:

[VHDL-FPGA-Verilog] CD-ROM-code-(verilog-hdl)

Description: 数字信号处理的fpga实现第2版-光盘源码（verilog HDL）-Fpga implementation of digital signal processing 2nd Edition- CD source (verilog HDL)
Platform: | Size: 356352 | Author: 周诚 | Hits:

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